aod418/AOI418 30v n-channel mosfet general description product summary v ds i d (at v gs = 10v) 36a r ds(on) (at v gs = 10v) < 7.5m ? r ds(on) (at v gs = 4.5v) < 11m ? 100% uis tested 100% r g tested symbol v ds v gs i dm i as , i ar e as , e ar t j , t stg symbol t 10s steady-state steady-state r jc maximum junction-to-case c/w c/w maximum junction-to-ambient a d 2.5 50 3 w power dissipation a p dsm w t a =70c 50 1.6 t a =25c power dissipation b p d 13.5 27 avalanche energy l=0.1mh c 36 28 t c =25c t c =100c a t a =25c i dsm a t a =70c 125 pulsed drain current c continuous drain current g i d continuous drain current the aod418/AOI418 uses advanced trench technology to provide excellent r ds(on) , low gate charge and low gate resistance. with the excellent thermal resistance of the dpak/ipak package, this device is well suited for high current load applications. v maximum units parameter absolute maximum ratings t a =25c unless otherwise noted 30v v 20 gate-source voltage drain-source voltage 30 mj avalanche current c 10.5 a 36 c thermal characteristics units maximum junction-to-ambient a c/w r ja 16 41 20 parameter typ max t c =25c 2.5 25 t c =100c junction and storage temperature range -55 to 175 to252 dpak top view bottom view g s d g s d g g d d s s to p view bottom view to251a ipak g d s rev 0: february 2011 www.aosmd.com page 1 of 6
aod418/AOI418 symbol min typ max units bv dss 30 v v ds =30v, v gs =0v 1 t j =55c 5 i gss 100 na v gs(th) gate threshold voltage 1.5 1.95 2.5 v i d(on) 125 a 6.2 7.5 t j =125c 9.5 11.5 g fs 63 s v sd 0.72 1 v i s 36 a c iss 920 1150 1380 pf c oss 125 180 235 pf c rss 60 105 150 pf r g 0.55 1.1 1.65 ? q g (10v) 16 20 24 nc q g (4.5v) 7.6 9.5 11 q gs 2.7 nc q gd 5nc t d(on) 6.5 ns t r 2ns t d(off) 17 ns t f 3.5 ns t rr 7 8.7 10.5 ns q rr 11 13.5 16 nc this product has been designed and qualified for the consumer market. applications or uses as critical components in life support devices or systems are not authorized. aos does not assume any liability arising out of such applications or uses of its products. aos reserves the right to improve product design, functions and reliability without notice. v gs =0v, v ds =15v, f=1mhz switching parameters body diode reverse recovery time gate resistance v gs =0v, v ds =0v, f=1mhz turn-off fall time total gate charge v gs =10v, v ds =15v, i d =20a electrical characteristics (t j =25c unless otherwise noted) static parameters parameter conditions drain-source breakdown voltage i d =250 a, v gs =0v v gs =10v, v ds =5v v gs =10v, i d =20a on state drain current forward transconductance diode forward voltage v gs =4.5v, i d =20a to252 i s =1a,v gs =0v v ds =5v, i d =20a static drain-source on-resistance v gs =10v, i d =20a to251a vgs=4.5v, i d=20a to251a i dss a v ds =v gs i d =250 a v ds =0v, v gs = 20v zero gate voltage drain current gate-body leakage current m ? to252 8.5 11 m ? body diode reverse recovery charge i f =20a, di/dt=500a/ s turn-on rise time turn-off delaytime i f =20a, di/dt=500a/ s maximum body-diode continuous current g input capacitance output capacitance turn-on delaytime dynamic parameters total gate charge gate source charge gate drain charge v gs =10v, v ds =15v, r l =0.75 ? , r gen =3 ? reverse transfer capacitance r ds(on) m ? m ? 6.7 8 9 11.5 a. the value of r ja is measured with the device mounted on 1in 2 fr-4 board with 2oz. copper, in a still air environment with t a =25c. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150c. the value in any given application depends on the user's specific board design, and the maximum temperature of 175c may be used if the pcb allows it. b. the power dissipation p d is based on t j(max) =175c, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. c. repetitive rating, pulse width limited by junction temperature t j(max) =175c. ratings are based on low frequency and duty cycles to keep initial t j =25c. d. the r ja is the sum of the thermal impedence from junction to case r jc and case to ambient. e. the static characteristics in figures 1 to 6 are obtained using <300 s pulses, duty cycle 0.5% max. f. these curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsi nk, assuming a maximum junction temperature of t j(max) =175c. the soa curve provides a single pulse rating. g. the maximum current rating is package limited. h. these tests are performed with the device mounted on 1 in 2 fr-4 board with 2oz. copper, in a still air environment with t a =25c. rev 0: february 2011 www.aosmd.com page 2 of 6
aod418/AOI418 typical electrical and thermal characteristic s 17 5 2 10 0 18 40 0 20 40 60 80 100 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 v gs (volts) figure 2: transfer characteristics (note e) i d (a) 2 4 6 8 10 12 0 5 10 15 20 25 30 i d (a) figure 3: on-resistance vs. drain current and gate voltage (note e) r ds(on) (m ? ) 1.0e-05 1.0e-04 1.0e-03 1.0e-02 1.0e-01 1.0e+00 1.0e+01 1.0e+02 0.0 0.2 0.4 0.6 0.8 1.0 1.2 v sd (volts) figure 6: body-diode characteristics (note e) i s (a) 25c 125c 0.8 1 1.2 1.4 1.6 1.8 2 0 25 50 75 100 125 150 175 200 temperature (c) figure 4: on-resistance vs. junction temperature (note e) normalized on-resistance v gs =4.5v i d =20a v gs =10v i d =20a 0 5 10 15 20 25 0246810 v gs (volts) figure 5: on-resistance vs. gate-source voltage (note e) r ds(on) (m ? ) 25c 125c v ds =5v v gs =4.5v v gs =10v i d =20a 25c 125c 0 20 40 60 80 100 120 140 012345 v ds (volts) fig 1: on-region characteristics (note e) i d (a) v gs =3v 3.5v 7v 10v 4v 4.5v 5v rev 0: february 2011 www.aosmd.com page 3 of 6
aod418/AOI418 typical electrical and thermal characteristic s 17 5 2 10 0 18 40 0 2 4 6 8 10 0 5 10 15 20 q g (nc) figure 7: gate-charge characteristics v gs (volts) 0 200 400 600 800 1000 1200 1400 1600 0 5 10 15 20 25 30 v ds (volts) figure 8: capacitance characteristics capacitance (pf) c iss 0 40 80 120 160 200 0.0001 0.001 0.01 0.1 1 10 pulse width (s) figure 10: single pulse power rating junction-to- case (note f) power (w) 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 pulse width (s) figure 11: normalized maximum transient thermal impedance (note f) z jc normalized transient thermal resistance c oss c rss v ds =15v i d =20a single pulse d=t on /t t j,pk =t c +p dm .z jc .r jc t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse t j(max) =175c t c =25c 10 s 0.0 0.1 1.0 10.0 100.0 1000.0 0.01 0.1 1 10 100 -v ds (volts) -i d (amps) figure 9: maximum forward biased safe operating area (note f) 10 s 10ms 1ms dc r ds(on) limited t j(max) =175c t c =25c 100 s r jc =3c/w rev 0: february 2011 www.aosmd.com page 4 of 6
aod418/AOI418 typical electrical and thermal characteristic s 17 5 2 10 0 18 40 0.001 0.01 0.1 1 10 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 pulse width (s) figure 16: normalized maximum transient thermal impedance (note h) z ja normalized transient thermal resistance single pulse d=t on /t t j,pk =t a +p dm .z ja .r ja t on t p d in descending order d=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse 0 10 20 30 40 50 60 0 25 50 75 100 125 150 175 t case (c) figure 13: power de-rating (note f) power dissipation (w) 0 10 20 30 40 50 0 25 50 75 100 125 150 175 t case (c) figure 14: current de-rating (note f) current rating i d (a) 0 20 40 60 80 100 0.00001 0.001 0.1 10 1000 pulse width (s) figure 15: single pulse power rating junction-to- ambient (note h) power (w) t a =25c r ja =50c/w 10 100 1 10 100 1000 time in avalanche, t a ( s) figure 12: single pulse avalanche capability (note c) -i ar (a) peak avalanche current t a =25c t a =150c t a =100c t a =125c rev 0: february 2011 www.aosmd.com page 5 of 6
aod418/AOI418 vdc ig vds dut vdc vgs vgs qg qgs qgd charge gate charge test circuit & waveform - + - + -10v vdd vgs id vgs rg dut vdc vgs vds id vgs unclamped inductive switching (uis) test circuit & waveforms vds l - + 2 e = 1/2 li ar ar bv dss i ar ig vgs - + vdc dut l vgs isd diode recovery test circuit & waveforms vds - vds + di/dt rm rr vdd vdd q = - idt t rr -isd -vds f -i -i vdc dut vdd vgs vds vgs rl rg resistive switching test circuit & waveforms - + vgs vds tt t t t t 90% 10% r on d(off) f off d(on) rev 0: february 2011 www.aosmd.com page 6 of 6
|
